This application claims benefit of priority to Provisional Application Ser. No. 60/224,368 filed Aug. 9, 2000.
1. Field of the Invention
This invention is related to the field of processors and, more particularly, to segmentation mechanisms in processors.
2. Description of the Related Art
The x86 architecture (also known as the IA-32 architecture) has enjoyed widespread acceptance and success in the marketplace. Accordingly, it is advantageous to design processors according to the x86 architecture. Such processors may benefit from the large body of software written to the x86 architecture (since such processors may execute the software and thus computer systems employing the processors may enjoy increased acceptance in the market due to the large amount of available software).
The x86 architecture includes a segmentation mechanism and a paging mechanism for performing address translation. Segment descriptors in a segment table provide a segment base address which is added to other operands of an instruction to produce a linear address, which may then be translated through a paging mechanism to a physical address. The segmentation mechanism provides for variable sized segments which may be arbitrarily located in memory. Unfortunately, such segments complicate memory management (particularly in a multitasking environment). The paging mechanism translates fixed size pages of virtual (linear) addresses to corresponding fixed sized pages of physical addresses, thus simplifying memory allocation and management. The segment descriptor may also include various access attributes used to control the allowable access to the segment (e.g. read/write) and to indicate the type of information stored in the segment (e.g. code/data/stack). Additionally, the paging mechanism includes access attributes as well.
In modern operating systems, the demand paged memory allocation model supported by the paging mechanism has become popular while the segmentation mechanism may be largely unused. Particularly, a “flat addressing” mode is frequently used in which the segment descriptors are programmed to a zero base address and a maximum limit. In this manner, the segments may be mapped to the entire linear address space, thus having no effect on the linear address. Effectively, only the paging mechanism is used in this mode. However, it is still desirable to provide compatibility with application programs which use segmentation.